Ahasan Ullah Khalid
RTL Design & Verification Engineer | VLSI Lecturer | RISC-V | FPGA | ASIC Design
About Me
Get to know more about my background, skills, and experience
Ahasan Ullah Khalid
RTL Design & Verification Engineer | VLSI Lecturer | RISC-V | FPGA | ASIC Design
📍 Dhaka, Bangladesh
Experience
RTL Design & Verification Engineer (Intern)
ADN Semiconductors Ltd.
RTL Design Projects with SystemVerilog HDL, verifying them with testbench and full ASIC/FPGA implementation for different clients.
VLSI Lecturer (Part-time)
Manarat International University (MIU)
Delivering comprehensive lectures and practical sessions on VLSI design for EEE department
Intern
Teletalk Bangladesh Ltd.
Industrial attachment, learned about how the networking works in circuit and packet switching.
Founder / Co-Owner
AshesToFlame Records
Managed music production, release workflow, branding, collaborations, artists/talents management.
Skills & Technologies
My Projects
A showcase of my recent work and side projects
EVPIX-RV32: Custom RISC-V SoC with IPU & TinyML Accelerators
A custom 32-bit, 5-stage pipelined RISC-V processor core featuring dedicated hardware accelerators and custom instruction extensions optimized for edge vision and real-time image processing tasks.
EVPIX-RV32: FPGA Implementation & Verification
Hardware validation and prototyping of the EVPIX-RV32 processor core on physical FPGA hardware. Includes testbench development, hardware-in-the-loop validation, and resource optimization utilizing Quartus II.
EVPIX-RV32: RTL-to-GDSII ASIC Flow Layout
Physical design and synthesis of the EVPIX-RV32 edge vision processor using an advanced open-source PDK flow. Covers the entire RTL-to-GDSII ASIC implementation pipeline including logic synthesis, floorplanning, placement, CTS, and routing.
SAP-1-CPU-Logisim
A complete implementation of the Simple-As-Possible (SAP-1) CPU architecture designed and simulated using Logisim Evolution. This project includes a hardwired control unit, enabling automated execution of machine code programs, demonstrated with an 8-bit addition operation.
CMOS-VLSI-Designs-gpdk90
A comprehensive collection of CMOS standard cells and digital system designs implemented using the gpdk90 open-source PDK in Cadence Virtuoso. Includes transistor-level schematics, layouts, symbols, and simulations in ADE L with verification against truth tables. Covers both fundamental gates (inverter, NAND, NOR, adders) and advanced circuits.
Nokshia
This is a website of a company called Nokshia. It's made of only HTML, CSS, Tailwind CSS, JS etc.
Get In Touch
Have a project in mind or want to collaborate? I'd love to hear from you!
Let's Connect
I'm always open to discussing new opportunities, creative projects, or just having a friendly chat about technology, chip design or maybe sports, anime etc.
aukhalid02@gmail.com
Phone
+8801610074044
Location
Dhaka, Bangladesh